diff --git a/arch/x86/cpu/intel_common/mrc.c b/arch/x86/cpu/intel_common/mrc.c
index 56cc253..ff959d1 100644
--- a/arch/x86/cpu/intel_common/mrc.c
+++ b/arch/x86/cpu/intel_common/mrc.c
@@ -9,6 +9,7 @@
 #include <dm.h>
 #include <init.h>
 #include <log.h>
+#include <spl.h>
 #include <syscon.h>
 #include <asm/cpu.h>
 #include <asm/global_data.h>
@@ -251,13 +252,28 @@
 int mrc_common_init(struct udevice *dev, void *pei_data, bool use_asm_linkage)
 {
 	struct udevice *me_dev;
-	int ret;
+	int ret, delay;
 
 	ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev);
 	if (ret)
 		return ret;
 
+	delay = dev_read_u32_default(dev, "fspm,training-delay", 0);
+	if (spl_phase() == PHASE_SPL) {
+		if (delay)
+			printf("SDRAM training (%d seconds)...", delay);
+		else
+			log_debug("SDRAM init...");
+	} else {
+		if (delay)
+			printf("(%d seconds)...", delay);
+	}
+
 	ret = sdram_initialise(dev, me_dev, pei_data, use_asm_linkage);
+	if (delay)
+		printf("done\n");
+	else
+		log_debug("done\n");
 	if (ret)
 		return ret;
 	quick_ram_check();
diff --git a/arch/x86/dts/chromebook_samus.dts b/arch/x86/dts/chromebook_samus.dts
index 96705ce..ddff277 100644
--- a/arch/x86/dts/chromebook_samus.dts
+++ b/arch/x86/dts/chromebook_samus.dts
@@ -266,6 +266,7 @@
 			board-id-gpios = <&gpio_c 5 0>, <&gpio_c 4 0>,
 					<&gpio_c 3 0>, <&gpio_c 1 0>;
 			bootph-all;
+			fspm,training-delay = <7>;
 			spd {
 				#address-cells = <1>;
 				#size-cells = <0>;